1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device in which a conductive layer and an SiO2 film on this conductive layer are simultaneously processed into a wiring pattern.
2. Description of the Related Art
FIG. 1 shows a related art of a method of manufacturing a MOS transistor in which a contact hole for the source/drain is formed in self-alignment with the gate electrode. In this related art, after an SiO.sub.2 film 12 serving as a gate oxide film is formed on the surface of an Si substrate 11, a polycide film 13 or the like serving as a gate electrode material, and an SiO.sub.2 film 14 serving as an offset insulating film are sequentially formed.
A resist 15 is coated on the SiO.sub.2 film 14, exposed in a gate electrode pattern with an i-line (wavelength: 365 nm), and then developed. The SiO.sub.2 film 14 and the polycide film 13 are simultaneously processed into the gate electrode pattern by etching using the resist 15 as a mask. After the resist 15 is removed, diffusion layers (not shown) for an LDD structure are formed in the Si substrate 11 by ion-implanting an impurity using the SiO.sub.2 film 14 and the like as a mask.
Sidewall spacers (not shown) are formed on the polycide film 13 and the SiO.sub.2 film 14, and a source and drain (not shown) are formed in the Si substrate 11 by ion-implanting an impurity using the SiO.sub.2 film 14, the sidewall spacers, and the like as a mask. An interlayer insulating film (not shown) is formed on the entire surface. Portions of the interlayer insulating film above and near the source and drain where contact holes are to be formed are selectively removed.
The above related art employs a film thickness of about 200 nm for the SiO.sub.2 film 14 in order to ensure a dielectric breakdown voltage across a conductive layer (not shown) on the SiO.sub.2 film 14 and the interlayer insulating film, and the polycide film 13, and to facilitate subsequent processing by suppressing an increase in step.
If, however, the SiO.sub.2 film 14 about 200 nm thick is used as an offset insulating film on the polycide film 13, so-called tails 15a are formed in the resist 15, as shown in FIG. 1. For this reason, it is difficult to form a gate electrode having a desired line width with high controllability.